1. Field of the Invention
The present application relates generally to an improved processor unit design. In particular, the present application relates to improved methods for reducing power consumption in processor units. Still more particularly, the present application relates to improved circuits for reducing a capacitive load on a global clock grid of a processor unit.
2. Description of the Related Art
Modern processor units, including those processor units used in personal computers, use extremely fast, precise clocks as timing mechanisms to aid in the transfer of data in the processor unit and in other computer components. These clocks operate on about the same scale as the processor unit cycles, which today are usually measured in gigahertz; or, one billion cycles per second.
Thus, the clocks in modern processor units keep time to about several hundred picoseconds or less. A picosecond is one-trillionth of a second.
In many cases, a “global clock” acts as a master timekeeper for the processor unit. However, with respect to the time periods in which processor units operate, the physical size of the processor unit, in conjunction with the speed at which signals propagate, can lead to skews in timing with respect to different parts of the processor unit. For example, as a theoretical limit, the speed of light is about one foot per nanosecond. A nanosecond is one billionth of a second. Thus, for a theoretical processor unit that was one foot across, a full nanosecond would be required to transmit a timing signal from one end of the processor unit to the other. Because the processor unit is operating at a speed of more than one cycle per nanosecond, this timing difference throughout the processor unit could result in major errors.
Although this example is extreme in a number of senses, the example conveys the nature of some of the real difficulties in timing operations within a processor unit. One method of addressing this problem has been to use local clock buffers on different physical parts of a processor unit. A local clock buffer uses the timing signal of the global clock to generate secondary time keeping signals that can be adjusted with respect to the global clock signal. The secondary time keeping signals are used by circuits located physically near the local clock buffer. In this manner, in further conjunction with placing multiple local clock buffers throughout a processor unit, a processor unit can more accurately track timing throughout the processor unit.
Local clock buffers usually have multiple outputs. Each output can be connected to a different circuit in the physical vicinity of the local clock buffer. Controlling, in a stable manner, which of these outputs are active in a given cycle is a challenging problem. An even greater problem is that the entire processor unit and each circuit within the processor unit (including the local clock buffers) should consume as little power as possible.